Method and system for accelerated access to a memory

ABSTRACT

Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of:  
     producing access requests ( 46, 47 ) defining each time a type of access and designating one or several memory locations ( 46   a - d   , 47   a - b ) arranged in accordance with a sequence suitable for said request,  
     processing the requests in accordance with a successive sequence so as to transfer, for each processed request, data from the designated memory location to the data processing circuit, or vice versa,  
     the processing of a request ( 46 ) designating memory locations ( 46   a,    46   b,    46   c,    46   d ) associated with several banks (A, B, A, B) authorizing a transfer of data between the interface and the memory locations in a sequence which is different from the sequence associated with said request.

[0001] The invention relates to a method of transferring data between adata processing circuit and a memory comprising several banks, notablyof the SDRAM type (Synchronous Dynamic Random Access Memory), a memoryinterface circuit, a computer program suitable to be executed by such aninterface circuit, and a data processing system.

[0002] Data processing systems are known which comprise a dataprocessing circuit, a memory comprising several banks and a memoryinterface circuit arranged between the data processing circuit and thememory for controlling the exchange of data between them.Conventionally, the data processing circuit executes one or severalfunctions necessitating access to the read memory for transferring thedata to be processed from the memory to the data processing circuit, orto the write memory for transferring processed data from the dataprocessing circuit to the memory. Every time, the data processingcircuit sends an access request to the interface circuit, i.e. a datatransfer command. The interface circuit processes the received requestsone by one by identifying a series of data and a transfer directiondefined by the processed request and by effecting the correspondingtransfer. In known manner, the preparation of an access operationcomprises an operation of pre-loading a file of large capacity of thecorresponding bank and an operation of activating the bank, such that itrequires several clock cycles.

[0003] These known systems have drawbacks: during execution of thesuccessive access commands, it may happen that an access operation whichis in progress is related to the same memory bank as the next accessoperation. In this case, a waiting time has to be observed for theaccess operation in progress to end before it is possible to prepare thenext access operation by preloading and/or activating the row that mustform the subject of an access operation. During this preparation, nodata transfer takes place with the memory so that the passband of thememory is used less efficiently the more frequently this situationoccurs.

[0004] It is an object of the invention to remedy the above-mentioneddrawbacks so as to improve the speed of access to a memory comprisingseveral banks and the efficiency of such a memory with regard to itscost.

[0005] To this end, the invention provides a method of transferring databetween a memory comprising several banks and a circuit for processingdata via an appropriate interface, said method comprising the steps of:

[0006] producing access requests defining each time a type of accessamong the read and write types and designating one or several memorylocations arranged in accordance with a sequence suitable for eachrequest,

[0007] processing the requests in accordance with a successive sequenceso as to transfer, for each processed request, data through theinterface from the memory location designated by said request to thedata processing circuit, or reciprocally, in accordance with the type ofaccess defined by the request,

[0008] the processing of a request designating memory locationsassociated with several banks authorizing a transfer of data between theinterface and the memory locations in a sequence which is different fromthe sequence associated with said request, so as to prepare the transferof data between the interface and one part of the memory locations atthe latest during the realization of the transfer of data between theinterface and another part of said memory locations.

[0009] The processing of a request designating memory locationsassociated with several banks comprises the steps of:

[0010] splitting up the request into several parts each designating oneor several memory locations associated with a single one of said banks,

[0011] successively processing said request parts so as to realize eachtime a corresponding transfer of data between the interface and thememory location designated by the part of the processed request bypreparing the transfer corresponding to one of the request parts at thelatest during the realization of the transfer corresponding to anotherone of said request parts.

[0012] As soon as an access request concerns several banks, the preloadand/or activation which is necessary for realizing a part of the accessother than the first part is always effected during the realization ofthe previous access part, i.e. by effecting a data transfer. Thepassband of the memory is thus better used.

[0013] Advantageously, each part of the request designates all thememory locations designated by the request and associated with adistinct bank. The duration of each access part is thus optimized whichis necessary for completely preparing a subsequent access part duringthe realization of a current access part.

[0014] Preferably, the processing of a request designating memorylocations associated with several banks also comprises the step of:

[0015] choosing a request part to be processed as the first part suchthat the memory location which it designates is associated with a memorybank which is different from the bank with which the memory locationdesignated by the request or the request part preceding immediately insaid successive processing sequence is associated, the processing of therequest part to be processed as the first part comprising a step ofpreparing the corresponding bank, said preparation being effected at thelatest during the processing of the request or request part immediatelypreceding.

[0016] In this way, a request concerning several banks is alwaysprocessed with a minimal delay or without delay after processing thepreceding request, while the pre-loading and/or activation necessary forrealizing the first part of the access operation is always effectedduring the realization of the preceding access operation. The use of thepassband of the memory is thereby further improved.

[0017] Advantageously, the processing of a request of the read typedesignating memory locations associated with several banks alsocomprises the steps of:

[0018] temporarily memorizing, in the interface, the data transferredfrom the memory during successive processing operations of the parts ofsaid request,

[0019] re-sequencing the data so as to transfer them to the dataprocessing circuit in accordance with the sequence of memory locationssuited for said request.

[0020] In this way, the method of transferring data does not affect theformat in any way in which the processing circuit receives the data thathave been read, while no particular measure needs to be taken as regardsthe processing circuit.

[0021] The invention also provides an interface circuit of a memorycomprising several banks intended to be connected to a data processingcircuit suitable for transmitting access requests to the interfacecircuit, the interface circuit being suitable for reading said accessrequests so as to identify each time a type of access among the read andwrite types, and one or several memory locations designated by saidrequest, the interface circuit being suitable for processing therequests in accordance with a successive sequence so as to transfer, foreach processed request, data from the memory location designated by saidrequest to the data processing circuit, or reciprocally, in accordancewith the identified type of access, said interface circuit includingmeans for processing a request designating memory locations associatedwith several banks by transferring said data between the interfacecircuit and the memory locations in a sequence which is different fromthe sequence suited for said request so as to prepare the transfer ofdata between the interface circuit and one part of memory locations atthe latest during the realization of the transfer of data between theinterface circuit and another part of said memory locations.

[0022] Such an interface circuit preferably comprises means for:

[0023] splitting up the request into several parts each designating oneor several memory locations associated with a single one of said banks,

[0024] successively processing said request parts so as to realize eachtime a corresponding transfer of data between the interface circuit andthe memory location designated by the part of the processed request,

[0025] preparing the corresponding transfer to one of the request partsat the latest during the realization of the corresponding transfer toanother one of said request parts.

[0026] Advantageously, this interface circuit also comprises means for:

[0027] choosing a request part to be processed as the first part suchthat the memory location which it designates is associated with a memorybank which is different from the bank with which the memory locationdesignated by the request or the request part preceding immediately insaid successive processing sequence is associated,

[0028] performing a step of preparing the bank corresponding to saidrequest part to be processed as the first part at the latest during theprocessing of the request or request part immediately preceding.

[0029] The interface circuit according to the invention preferably alsocomprises means for:

[0030] temporarily memorizing the data transferred from the memoryduring successive processing operations of the parts of a request of theread type designating memory locations associated with several banks,

[0031] re-sequencing the data so as to transfer them to the dataprocessing circuit in accordance with the sequence of memory locationssuited for said request.

[0032] The invention also provides a computer program comprisinginstruction codes suitable to be read or stored on a record carrier,said instruction codes being suitable to be executed by a programmableinterface circuit intended to be connected to a memory comprisingseveral banks and to a data processing circuit suitable for sendingaccess requests to the interface circuit, the execution of saidinstruction codes being suitable for performing the following steps onthe interface circuit:

[0033] reading the access requests so as to identify each time a type ofaccess from the read and write types and one or several memory locationsdesignated by said request,

[0034] processing the requests in accordance with a successive sequenceso as to transfer, for each processed request, data from the memorylocation designated by said request to the data processing circuit, orreciprocally, in accordance with the identified type of access,

[0035] the processing of a request designating memory locationsassociated with several banks authorizing a transfer of data between theinterface and the memory locations in a sequence which is different fromthe sequence associated with said request, in order to prepare thetransfer of data between the interface and one part of the memorylocations at the latest during the realization of the transfer of databetween the interface and another part of said memory locations.

[0036] The invention also provides a data processing system comprising:

[0037] a memory comprising several banks,

[0038] a data processing circuit suitable for producing access requests,each access request defining a type of access among the read and writetypes and designating one or several memory locations,

[0039] an interface suitable for processing the requests in accordancewith a successive sequence so as to transfer, for each processedrequest, data from the memory location designated by said request to thedata processing circuit, or reciprocally, in accordance with the accesstype defined by the request,

[0040] in which system the interface is suitable for realizing theprocessing of a request designating memory locations associated withseveral banks by transferring the data between the interface and thememory locations designated by said request in a sequence which isdifferent from the sequence associated with said request so as toprepare the transfer of data between the interface and one part of thememory positions at the latest during the realization of the transfer ofdata between the interface and another part of said memory locations.

[0041] Said interface is preferably suitable for:

[0042] splitting up a request designating memory locations associatedwith several banks into several parts each designating one or severalmemory locations associated with a single one of said banks,

[0043] successively processing said request parts so as to realize eachtime a corresponding transfer of data between the interface and thememory location designated by the part of the processed request

[0044] preparing the transfer corresponding to one of the request partsat the latest during the realization of the transfer corresponding toanother one of said request parts.

[0045] The invention relates to access operations to any memory of theSDRAM or another type, comprising several banks, in which the access toa bank may be prepared while another bank is being accessed.

[0046] These and other aspects of the invention are apparent from andwill be elucidated, by way of non-limitative example, with reference tothe embodiment(s) described hereinafter.

[0047] In the drawings:

[0048]FIG. 1 shows diagrammatically a data processing system accordingto the invention,

[0049]FIG. 2 shows diagrammatically a programmable memory interfacecircuit according to the invention,

[0050]FIG. 3 shows a sequence of bits coding a memory address of thesystem of FIG. 1,

[0051]FIG. 4 is an address mapping of the memory of the system shown inFIG. 1,

[0052]FIGS. 5a to 5 c illustrate three steps of pre-processing a requestfor access by the memory interface circuit shown in FIG. 2,

[0053]FIGS. 5d and 5 e illustrate two steps of post-processing a readrequest by the memory interface circuit shown in FIG. 2,

[0054]FIG. 6a shows the development with respect to time of two accessoperations processed without the pre-processing steps shown in FIGS. 5ato 5 c,

[0055]FIG. 6b shows the development with respect to time of two accessoperations processed with the pre-processing steps of FIGS. 5a to 5 c,

[0056]FIG. 7 shows the development of a preload of a bank designated byan access request of a central unit during the realization of an accessoperation of a data processing circuit within the system shown in FIG.1,

[0057]FIG. 8 shows the development of a write access operation by thecentral unit interrupting a write access operation by a data processingcircuit,

[0058]FIG. 9 shows the development of a read access operation by thecentral unit interrupting a read access operation by a data processingcircuit,

[0059]FIG. 10 shows the development of a write access operation by thecentral unit interrupting a read access operation by a data processingcircuit,

[0060]FIG. 11 shows the development of a read access operation by thecentral unit interrupting a write access operation by a data processingcircuit.

[0061] The data processing system shown in FIG. 1 comprises a memory 1of the SDRAM type comprising four banks A, B, C and D. The memory 1 isconnected to a memory interface circuit 2 comprising a buffer memory 3.The interface circuit 2 is connected to a central unit 4 comprising alogic and arithmetic unit 5 and a controller 6, and to a data processingcircuit 7. For example, the data processing circuit 7 is a processordedicated to processing audio, video and graphic (AVG) data such as datain the MPEG format (Motion Picture Expert Group).

[0062] The central unit 4 is connected to the interface circuit 2 byconnection means 8 comprising a data bus, an address bus and commandlines. The data processing circuit 7 is connected to the interfacecircuit 2 by connection means 9 also comprising a data bus 15, anaddress bus and command lines 16, which can be seen in FIG. 2. A datainterface module 40 is connected to the data bus 15 and ensures thereception and transmission of AVG data from the interface circuit 2.

[0063] The interface circuit 2 is connected to the memory 1 byconnection means 17 comprising a data bus 10, an address bus 11, twobank selection lines 12 and 13 and command lines 14. A mask command DQMalso allows selection of a part of each memory location which isaccessed when the data to be read or written are shorter than the memoryword. A memory word is made up of, for example, 32 bits.

[0064] The memory 1 is a collective memory in which the central unit 4performs access operations for reading and writing data and instructioncodes and in which the data processing circuit 7 performs accessoperations for reading and writing the AVG data. Per design of thememory 1, a single access operation may be performed simultaneously. Thecentral unit 4 and the data processing circuit 7 access the memory 1,both for writing and reading, by way of the interface circuit 2 byproducing an access request sent to the interface circuit 2, i.e. atransfer command to be executed by the interface circuit 2.

[0065] In a variant, several analog data processing circuits eachproduce requests for access to the memory 1. In this case, the differentdata processing circuits communicate with the interface circuit 2 via acommon data central unit which transmits in known manner the accessrequests and the corresponding data between the data processing circuittransmitting the request and the interface circuit 2. In this case, theblock 7 of FIG. 1 is considered to represent a set of data processingcircuits and their common data central unit.

[0066] Per design of the memory 1, an access operation is performed inone or several bursts of consecutive locations in one or several banks.In the embodiment under consideration, the requests of the dataprocessing circuit 7 refer each time to 16 memory words representing,for example, pixel values of a portion of the image. The requests by thecentral unit may refer to 1, 4 or 8 memory words.

[0067] An access request designates a set of memory locations that mustform the subject of an access and defines a series of data to betransferred and a transfer direction to be effected. For example, thetransfer direction is defined by the high or low positioning of one orseveral specific input registers of the interface circuit 2. A series ofdata to be read is designated by an address in the memory 1. A series ofdata to be written is designated by a signal on a data bus at the inputof the interface circuit 2. The memory locations that form the subjectof an access are defined by the following parameters: an address of afirst location of a first block to be read or written in the memory 1, anumber of blocks to be read or written, a number of locations to beskipped between each block and a number of consecutive memory locationsto be read or written in each block. Of course there may also be asingle block of contiguous locations. An address comprises a banknumber, a row number and a column number.

[0068] The interface circuit 2 treats each access request in such a waythat the defined series of data is transferred from the source of therequest to the memory locations thus defined, or from the locations thusdefined to the source of the request, according to whether a write or aread request is concerned.

[0069] The operation of the memory interface circuit 2 will now bedescribed with reference to FIG. 2. A processing phase which is specificfor the access requests sent by the data processing circuit 7 will bedescribed first.

[0070] The interface circuit 2 comprises an arbitration module 18connected to the command lines 16 and dedicated to the arbitration ofthe access requests sent by the processing circuit or circuits 7. Thearbitration module 18 applies a certain arbitration procedure so as todetermine the order in which the access requests that are in the queueand emanate from the processing circuit or circuits 7 must be executed.At the start of this procedure, an access request 42 is accepted andtransmitted to a pre-processing module 19 by means of a commandregister, whereafter the remaining requests in the queue arere-arbitrated.

[0071] For example, the accepted access request 42 is coded in thiscommand register in the following manner: the eight least significantbits designate a number of memory words to be skipped between each blockof data to be read or written, the four subsequent bits designate anumber of consecutive memory words per block, the next bit designatesthe type of access among the types of reading and writing and thesubsequent bits designate the address of a first memory word of a firstblock to be read or written in the memory 1.

[0072] The pre-processing module 19 applies a procedure in two steps tothe access request 42 received from the circuit or from one of thecircuits 7:

[0073] in a regrouping step, the number of different banks concerned forthe access request is computed. When the access request concerns severalbanks, it is divided into as many parts of access requests. Each requestpart designates all the memory locations designated by the request andbelonging to a different bank.

[0074] in a sequencing step, the pre-processing module 19 sequences therequest parts produced from the pre-processed request so as to preventthat two parts of the executed request successively concern one and thesame bank. To this end, it determines the bank concerned for the lastpart of the request immediately preceding the request duringpre-processing and places a part of the request designating a differentbank at the first location.

[0075] As soon as the part or parts of the request 21 supplied from theaccess request are available, each with a designated bank number, thenumber of the row designated in the bank, the number and the list ofcolumns designated in the row and an indicator of the access type, theyare transmitted to a column generator 20 in the order determined above.The column generator 20 is dedicated to the access requests of the dataprocessing circuit 7.

[0076] The pre-processing module 19 sends a signal 23 to a collisionmanager 22, which signal indicates the presence of a part of the requestready to be executed.

[0077] A processing phase which is specific for the access requests sentby the central unit 4 will now be described. An access request from thecentral unit 4 is received by a central unit interface module 28connected to the connection means 8. The interface module 28 comprises aqueue which contains only a single request waiting to be processed. Theinterface module 28 waits until the request which is in the process ofbeing processed is ended before it accepts the next request. A requestfor access to the memory 1 coming from the central unit 4 alwaysconcerns a series of consecutive addresses, i.e. it does not comprise askipped location. When it accepts a request, the interface module 28transmits a signal 29 to the collision manager 22 indicating thepresence of a central unit request which is ready to be executed and ittransmits the accepted request 33 to a column generator 30 dedicated tothe access requests of the central unit 4.

[0078] The collision manager 22 has the function of arbitrating betweenthe parts of the request and the central unit requests which are readyto be executed. The collision manager 22 manages the realization ofaccess operations requested by the central unit 4 and the dataprocessing circuit or circuits 7 so as to process the requests whichhave first priority. Indeed, the AVG data are considered as ordinarydata, in contrast to the data and instruction codes of the central unit4 which are considered as priority data. In order to operate, thecollision manager 22 generates activation signals 24 and 34 destined forthe column generators 20 and 30, respectively, in accordance with apredetermined method.

[0079] A processing phase which is common for all the requests will nowbe described. The column generators 20 and 30 are activated by thereception of the activation signal 24 or 34 of the collision manager 22.Upon reception of the corresponding activation signal, the columngenerator 20 or 30 processes the part or parts 21 of the request of thedata processing circuit or the request of the central unit 33,respectively, by translating it into a series of column numbers 31, orinto a series of column numbers 32, respectively, so as to form accessdemands at an appropriate detailed level for a command generator 25(numbers of bank, row and column of each memory location concerned bythe part of the request or by the request of the central unit,respectively). In co-operation with the activated column generator 20 or30, the command generator 25 also generates a succession of elementaryaccess commands, each elementary command defining an operation of accessto a single address.

[0080] The command generator 25 also produces commands which arenecessary for preparing access operations to be performed, such aspreload commands for the bank concerned and activation of the rowforming the subject of an access operation. The command generator 25also ensures the production of commands which are necessary for regularrefreshing of the memory 1, for example, of the order of 64 refreshesper millisecond.

[0081] A signal generator 26 generates command signals on the lines 14,which signals are specific for the memory 1, for example, RAS, CAS andWE signals which are known to those skilled in the art, as a function ofthe commands 27 sent by the command generator 25. Each data item of theseries defined by the request is transferred by the data bus 10 betweena memory location of the memory 1 and the buffer memory 3. For each dataitem, the bank is selected by positioning the bank selection lines 12and 13, and the row and column numbers are selected by the address bus11. The interface 2 also comprises a module for monitoring the state ofthe banks 54, which module generates signals indicating the state ofeach bank and its activity.

[0082] Other characteristic features of the data processing system shownin FIG. 1 will now be described with reference to FIGS. 3 and 4.

[0083]FIG. 3 shows a sequence 35 of 24 coding bits of an address of thememory 1 as designated in an access request received by the interfacecircuit 2. Each coding bit is individually marked by a weight rangingfrom 0 to 23, respectively. FIG. 3 also shows the interpretation of eachbit of the sequence 35 by the interface circuit 2. In the example shown,the memory 1 is supposed to be a SDRAM memory having a total capacity of64 Mo, with four banks of 256 columns by 2048 rows each. Consequently, acolumn number is coded at 8 bits, a row number at 11 bits and a banknumber at 2 bits, a complete address being coded at 2+11+8=21 bits. Itis of course also possible to use banks having a different row and/orcolumn number by adapting the number of bits used for coding thecorresponding number. It is also possible to use two identical SDRAMmemory units for the memory 1, having four banks each and, in acorresponding way, to lengthen the addresses of a selection bit of thememory unit. In practice, the addresses are normalized at 32 bits, inwhich the excess most significant bits denoted by the reference numeral36 are not used.

[0084] As is shown in FIG. 3, the interface circuit 2 converts anaddress in an access request coming from the processing circuit 7 orfrom the central unit 4 by means of the following method: the bank isdetermined by a binary code of two bits formed, in a decreasing order ofweight, by bits having a weight of 20 and 3, respectively, of thesequence 35, hereinafter denoted by B1 and B0, respectively. The columnnumber is determined by a binary code of eight bits formed, in adecreasing order of weight, from bits having weights of 8, 7, 6, 5, 4,2, 1 and 0, respectively, of the sequence 35. The row number isdetermined by a binary code of eleven bits formed, in a decreasing orderof weight, from bits having weights of 19 to 9, respectively, of thesequence 35.

[0085] The banks are selected in the following manner: the selection bitof the bank B1 designates either the couple of banks A-B (low value) orthe couple of banks C-D (high value). Within the respective couples, theselection bit of the bank B0 designates either the bank A, or C (lowvalue), respectively, or the bank B or D (high value), respectively.

[0086] In the system of FIG. 1, the data processing circuit 7 and thecentral unit 4 are designed in such a way that they read or write thedata which belong to them in a different couple of A-B or C-D banks. Forexample, the AVG data belonging to the data processing circuit 7 arewritten, read and memorized in the couple of banks A-B, the bit B1 beingalways positioned at its low value in the addresses designated by theaccess requests of the data processing circuit 7. Reciprocally, the databelonging to the central unit 4, for example, command instructions, arewritten, read and memorized in the couple of banks C-D, the bit B1 beingalways positioned at its high value in the addresses designated by thecorresponding access requests of the central unit 4.

[0087] Consequently, with reference to FIG. 4, the address mapping ofthe memory 1 is as follows. In an increasing order of addresses,represented by the axis 37, the memory 1 has a first zone 38 dedicatedto the data belonging to the data processing circuit 7 and constitutedby an alternation of blocks of banks A and B, each block having a lengthL of 8 words, and a second zone 39 dedicated to the data belonging tothe central unit 4 and constituted by an alternation of blocks of thebanks C and D of the same length L.

[0088] A request of the data processing circuit 7 designates a series ina sequence of sixteen addresses of the first zone 38 of the memory, forexample, in the form of a number of blocks, a number of words per blockand a number of locations to be skipped between each block. Because ofthe mapping of the memory 1, these sixteen addresses may be distributedin an arbitrary manner between the banks A and B. In the frequent casewhere a request designates sixteen consecutive addresses, they alwayscorrespond to locations which have been evenly distributed between thebanks A and B. This particular feature reduces the probability ofoccurrence of a sequence of two requests or two consecutive parts ofrequests designating one and the same bank.

[0089] As the conversion of the addresses in memory locations iseffected by the interface circuit 2, the addressing mode used by thecentral unit 4 and the processing circuit 7 do not need to be modifiedfor realizing the mapping of memory 1. This addressing mode may thusremain compatible with other components with which the central unit 4and the processing circuit 7 must communicate.

[0090] The pre-processing of the requests by the pre-processing module19 will now be explained in greater detail with reference to FIGS. 5a to5 c.

[0091]FIG. 5a diagrammatically shows the access request 42 received fromthe arbitration module 18 by the pre-processing module 19. The firstline indicates the number of columns that form the subject of an accessoperation in a certain row specified by the request. The second lineindicates the bank to which each column belongs. It is supposed that thecolumns designated c1 to c16 of the memory 1 comprise data d1 to d16.

[0092] With reference to FIG. 5b, the pre-processing module 19 reads thenumbers of the sixteen columns designated by the request 42 in the orderin which they are designated and, for each column, sends a numberencoded on one bit of the bank in which the column is present (forexample 0 for the bank A and 1 for the bank B) to the interface module40 through a queue 41. The pre-processing module 19 also determines thenumber of different banks designated in the request.

[0093] With reference to FIG. 5c, the pre-processing module 19 comprisesa state indicator 44 indicating the number of the bank in which the lastcolumn is situated which is designated by the last request or part ofthe request which it has pre-processed previously, which is now beingprocessed by the command processor 25 or is queuing behind an accessrequest of the central unit. The state indicator 44 indicates the bank Ain FIG. 5c. When the request 42 designates several banks, i.e. A and Bin the example shown, the pre-processing module 19 re-sequences thecolumns of the request 42 by regrouping them per associated bank into asmany column series. The column series belonging to a bank different fromthat indicated by the state indicator 44, i.e. belonging to bank B inthe example shown, is placed first. The series of column numbers c2 andc4 to c16 designated, in this order, in the request 42 and belonging tobank B is thus processed as a first part of the request 21 a. The seriesof column numbers c1 and c3 designated, in this order, in the request 42and belonging to bank A is processed as a second part of the request 21b. The request parts 21 a and 21 b are transmitted, in this order, tothe column generator 20, as has been explained hereinbefore.

[0094] A phase of post-processing requests of the read type of the dataprocessing circuit 7 by the interface module 40 will now be elucidatedwith reference to FIGS. 5d and 5 e. It is supposed that the request 42processed is of the read type.

[0095] With reference to FIG. 5d, the processing of the first part ofthe request by the command generator 25 involves reading of the data inthe order in which the columns have been designated to the columngenerator 20. The first data item transferred to the interface circuit 2is thus d2, which was memorized in the column c2. As from the arrival ofa data item read, the interface module 40 reads an address availablefrom the buffer memory 3 in a queue 43 comprising all the availableaddresses and temporarily stores the received data item d2 at thisaddress @1. The interface module 40 also comprises two address queues 45a and 45 b dedicated to the data from the banks A and B, respectively.The state indicator 44 now indicates the bank B in which the data arebeing read. The interface module 40 thus copies the storage address @1in the queue 45 b dedicated to the data from the bank B. This process isrepeated for the whole series of data d1 to d16 defined by the request42.

[0096] With reference to FIG. 5e it is supposed that all the data havebeen transferred from the memory 1 into the buffer memory 3 of theinterface circuit 2. The address queues 45 a and 45 b are shown in theirfinal state. The interface module 40 ensures the re-sequencing of thereceived data. To this end, the queue 41 is read. At each bank numberread, the interface module 40 reads the first address of the queuededicated to the data from the corresponding bank, i.e. first theaddress 15 in queue 45 a, because the first bank number read is 0. Itreads the data item stored at the address @15, which is the data itemd1, and transmits it on the data bus 15 to the processing circuit 7. Theaddress @15 is released and reset in the queue 43. This process isrepeated for all the bank numbers of the queue 41 until a signal is readwhich indicates that the last column of the request has been reached.The request is then terminated. The data are thus transferred to theprocessing circuit 7 in the order of the memory locations defined by therequest 42.

[0097] For a write request, the interface module 40 performs apre-processing operation which is symmetrical to the post-processingoperation described hereinbefore. During the execution of a part of therequest or of a request from the current central unit (current access),the command generator 25 examines the parameters of a part of therequest or of a subsequent request of the central unit under preparation(subsequent access). When the subsequent access refers to a bank whichis different from the bank concerned by the current access, the commandgenerator 25 generates the preload and activation commands of the bankconcerned by the subsequent access during the execution of the currentaccess in such a way that no clock cycle is lost for preparing thesubsequent access. To this end, the command generator 25 generates thecommands which correspond to the signals which it receivessimultaneously from the column generators 20 and 30 and from thecollision manager 22 in the following order of decreasing priority:

[0098] 1—preload of a bank designated by a request of the central unit,

[0099] 2—activation of a bank designated by a request of the centralunit,

[0100] 3—generation of an elementary access command for the centralunit,

[0101] 4—generation of an elementary access command for the processingcircuit 7,

[0102] 5—activation of a bank designated by a request of the processingcircuit 7,

[0103] 6—preload of an arbitrary bank,

[0104] 7—neutral command.

[0105]FIGS. 6a and 6 b illustrate a reduction of the access timesobtained by virtue of pre-processing requests by the interface circuit2. It is supposed that two requests 46 and 47 of the processing circuit7 are processed consecutively without a request from the central unit 4occurring. The request 46 designates, in this order, a batch 46 a ofeight columns of the bank A, a batch 46 b of three columns of the bankB, a batch 46 c of two columns of the bank A and a batch 46 d of threecolumns of the bank B. The request 47 designates, in this order, a batch47 a of eight columns of the bank B and a batch 47 b of eight columns ofthe bank A.

[0106]FIG. 6a illustrates the progress with respect to time ofprocessing the requests 46 and 47 if the requests are executed withoutpre-processing. The realization of an access operation to a banknecessitates an operation of preparing the access by pre-loading of thebank and by activating the row forming the subject of an accessoperation. This preparation requires a time At which has a value of, forexample, 6 clock cycles of the SDRAM memory. The preparation of thesubsequent access operation is performed from the start of the transferof data corresponding to the current access. However, the transferscorresponding to the batches of the columns 46 b and 46 c are shorterthan the preparation time Δt, such that a delay is lost before thetransfers corresponding to the batches 46 c and 46 d. Moreover, therequest 47 starts with an access operation in the bank B in which thelast column accessed in the course of the access operation 46 ispresent. A delay At is thus lost during the preparation of the bank Bbetween the processing of two requests.

[0107]FIG. 6b illustrates the progress with respect to time ofprocessing of the requests 46 and 47 with the pre-processing operationby the module 19. The transfer commands of data corresponding to thecolumn batches 46 a and 46 c are regrouped into a first request part 48and are consecutively processed in such a way that the delay lost beforeprocessing of the batch 46 c is suppressed. The commands for datatransfers corresponding to the column batches 46 b and 46 d areregrouped into a second request part 49 and are consecutively processedin such a way that the delay lost before processing the batch 46 d issuppressed. The request 47 is processed in two request parts 50 and 51designating the column batch 47 a and the column batch 47 b,respectively, by starting with the part 51 designating the column batch47 b, such that the operation of the corresponding transfer of databetween the bank A and the interface circuit 2 is prepared during therealization of the transfer corresponding to the request part 49. Thedelay lost between processing of the two requests 46 and 47 is thus alsosuppressed. The time required for processing the two requests is thussubstantially reduced, for example, by the order of 30% with respect tothe case where the pre-processing operation is not performed.

[0108] The arbitration of the access operations by the collision manager22 will now be described in greater detail with reference to FIGS. 7 to11. All of these Figures show the development as a function of time t ofone or several access operations of different types. Each column of thetables shown corresponds to a clock cycle of, for example, 8 ns of theSDRAM memory. The first line of the tables represents the transmissionof certain preparation commands of the SDRAM on the command lines 14. Apreload command is symbolized by PRE. An activation command issymbolized by ACT. The second line of the tables represents thetransmission of elementary read or write commands on the command lines14. An elementary read or write command requested by the data processingcircuit is symbolized by TR and TW, respectively. An elementary readcommand or write command required by the central unit is symbolized byCR and CW, respectively. An access request designating several memorylocations is translated into several successive elementary commandsenumerated as from 0. The third line of the tables represents the datain the course of their transfer on the data bus 10. A data itemtransferred while executing an elementary read or write command issymbolized by the letter D followed by the symbol of the correspondingelementary command.

[0109] With reference to FIG. 7, when the collision manager 22 receivesthe signal 29 during realization of an access operation of the dataprocessing circuit 7 and the bank designated by the request of thecentral unit 33 must be pre-loaded, it gives the command generator 25 acommand to insert a preload command between two elementary commands forthe access operation which is in progress, as is shown by means of thearrow 59. The collision manager 22 suspends the generation of theelementary access commands so as to release the command lines of thememory in order that a preload command can be transmitted. To this end,the column generator 20 activates a standby signal 52 throughout theduration by which the generation of the elementary commands must besuspended, i.e. for example, during a clock cycle. The collision manager22 commands the restart of generating the elementary access commands bytransmitting the activation signal 24 to the column generator 20 oneclock cycle before said restart, which reinitializes the standby signal52.

[0110] With reference to FIG. 8, it is supposed that a write access ofthe data processing circuit 7 is activated by the activation signal 24and is being realized when the central unit 4 requests a write access.An activation command of the bank designated by the request of thecentral unit is produced during the realization of the access operationin progress, i.e. during the transmission of the elementary command TW3in the example shown. It is noted that an activation command producesthe copy of a row of the SDRAM in a register in which the individualcolumns can be subsequently read or written and that its execution takesseveral, for example, two clock cycles. As soon as the activation isterminated, i.e. at the third clock cycle subsequent to the activationcommand in the example shown, the access operation which is in progressis suspended by the standby signal 52. In the example shown, the accessoperation which is in progress is suspended after the transmission ofthe elementary command TW5. The write access of the central unit islaunched by the activation signal 34. During production of the lastelementary access command for the access operation requested by thecentral unit, i.e. the elementary command CW7, the column generator 30sends an end-of-access signal 53 to the manager 22, which leads to thetransmission of an activation signal 24 and the re-initialization of thestandby signal 52. The generation of the elementary access commands forthe suspended access operation is resumed as from the subsequent clockcycle, with the subsequent elementary command TW6. By this sequence ofelementary commands, a transfer of data is effected at each clock cyclewithout any loss of passband.

[0111] With reference to FIG. 9, a read access operation of the dataprocessing circuit 7 is launched by the transmission of the activationsignal 24, and then the collision manager receives the signal 29. As inthe previous case, an activation command of the bank designated by therequest of the central unit 4 is transmitted during the realization ofthe access operation of the circuit 7, i.e. during the transmission ofthe elementary command TR2. The signals 24, 34 and 52 are then managedas described previously for inserting the access operation of thecentral unit by temporarily suspending the access operation of thecircuit 7. During a write access operation, the data to be written aresent on to the data bus 10 in the same clock-cycle as the transmissionof the corresponding elementary commands. In contrast, during a readaccess operation, there is a delay between the transmission of anelementary command and the transfer of the corresponding data itembecause of a delay of access to the individual columns LC which areintrinsic in the memory 1, and referred to as latency CAS. This delayis, for example, 3 clock cycles.

[0112] The module 54 for monitoring the state of the banks comprises,for each bank, an access indicator which is activated at the start ofeach access operation in this bank and reinitialized at the end of theaccess operation. In the example shown, the access indicator 55 is thatfor the bank, for example, A in which the data are read by the dataprocessing circuit 7 and the access indicator 56 is that for the bank,for example, C designated by the request of the central unit 4.

[0113] With reference to FIG. 10, an elementary command sequence isshown which is produced in the case where a write access request of thecentral unit 4 is produced during a read access operation of the circuit7. To allow transition of a read access to a write access, the data bus10 of the memory must pass from an output state to an input state. Thischange of states is performed by transistors of the bus 10 which, toavoid any risk of short-circuit, pass through a state of strongimpedance represented by the symbol HIZ in which no transfer of data canbe effected on the bus 10. This transmission requires a delay of oneclock cycle. The access of the central unit starts as soon as theactivation is terminated at the third clock cycle subsequent to thecommand ACT, while the transition through the state HIZ is effected justbefore, i.e. at the second clock cycle subsequent to the command ACT.The last data item read which can thus be transferred on the bus 10 isthat transferred at the first clock cycle subsequent to the command ACT.As the latency CAS is three clock cycles, this data item corresponds tothe elementary command transmitted in the second clock cycle precedingthe command ACT, i.e. the command TR0 in the example shown.Consequently, it is useless to produce read commands from the firstcycle preceding the transmission of the command ACT. In fact, theelementary access commands for the access operation to be suspended arereplaced by neutral commands NOP based on the command ACT until thestart of the access operation of the central unit. However, theelementary access command immediately preceding the command ACT, i.e.TR1, is produced without having the time to be executed before thesuspension of the access operation. Consequently, in this case, thesuspended access operation is resumed as soon as the completion of theaccess operation of the central unit by the retransmission of thecommand TR1 that has not been executed. To this end, the collisionmanager 22 updates counters of the column generator 20 during itsreactivation. The number of elementary commands to be retransmitted mustevidently be adapted as a function of the characteristic features of thememory used in each particular realization.

[0114]FIG. 11 shows a sequence of elementary commands produced when aread access operation of the central unit 4 suspends a write accessoperation of the circuit 7. In this case, the transition to the stateHIZ must be effected at the end of the access operation of the centralunit. However, to allow the transfer of all the data read by the centralunit, a delay which is equal to the latency CAS, i.e. three clock cyclesin the example shown, must be left between the production of the lastread command CR7 and the transition to the state HIZ. During this delay,the column generator 20 is in a standby position. The suspended accessoperation is resumed immediately after the transition.

[0115] To respect this delay, the module 54 for monitoring the state ofthe banks is provided with a counter 58 whose value at each clock cycleis indicated in the third line of the table in FIG. 11. The counter 58is positioned at a value which is equal to LC+1, i.e. the value 4 in theexample shown, whenever an elementary read command is transmitted. Thecounter 58 is decremented by one unit every time when no elementary readcommand is transmitted. As soon as it reaches the value of zero, asignal 57 is produced by the module 54, as is shown in FIG. 2, so as toindicate to the command generator 25 that the transition to the stateHIZ may be effected, and this immediately.

[0116] Although the invention has been described with reference to aparticular embodiment, it will be evident that it is by no means limitedand that it comprises all the equivalent techniques of the meansdescribed as well as their combinations if they are within the scope ofthe invention. There are actually numerous ways of performing thefunctions by means of hardware elements and/or computer programelements. In this respect, the Figures are very diagrammatic, eachFigure representing a single embodiment. Although a Figure may showvarious functions in the form of separate blocks, it does not excludethat a function may be performed by several separate blocks.

1. A method of transferring data between a memory (1) comprising severalbanks (A-D) and a circuit (7) for processing data via an appropriateinterface (2), said method comprising the steps of: producing accessrequests (42, 46, 47) defining each time a type of access among the readand write types and designating one or several memory locations (c1-c16,46 a-d, 47 a-b) arranged in accordance with a sequence suitable for eachrequest, processing the requests in accordance with a successivesequence so as to transfer, for each processed request, data through theinterface from the memory location designated by said request to thedata processing circuit, or reciprocally, in accordance with the type ofaccess defined by the request, the processing of a request (46)designating memory locations (46 a, 46 b, 46 c, 46 d) associated withseveral banks (A, B, A, B) authorizing a transfer of data between theinterface and the memory locations in a sequence which is different fromthe sequence associated with said request, so as to prepare the transferof data between the interface and one part (46 b, 46 d) of the memorylocations at the latest during the realization of the transfer of databetween the interface and another part (46 a, 46 c) of said memorylocations.
 2. A method as claimed in claim 1 wherein the processing of arequest (46) designating memory locations (46 a, 46 b, 46 c, 46 d)associated with several banks (A, B, A, B) comprises the steps of:splitting up the request into several parts (48; 49) each designatingone or several memory locations (46 a, 46 c; 46 b, 46 d) associated witha single one (A; B) of said banks, successively processing said requestparts so as to realize each time a corresponding transfer of databetween the interface and the memory location designated by the part ofthe processed request by preparing the transfer corresponding to one(49) of the request parts at the latest during the realization of thetransfer corresponding to another one (48) of said request parts.
 3. Amethod as claimed in claim 2, wherein each request part (48; 49)designates all the memory locations (46 a, 46 c; 46 b, 46 d) designatedby the request (46) and associated with a distinct bank (A; B).
 4. Amethod as claimed in claim 2, wherein the processing of a request (47)designating memory locations (47 a, 47 b) associated with several banks(B, A) also comprises the step of: choosing a request part to beprocessed as the first part (51) such that the memory location which itdesignates (47 b) is associated with a memory bank (A) which isdifferent from the bank (B) with which the memory location (46 b, 46 d)designated by the request or the request part (49) preceding immediatelyin said successive processing sequence is associated, the processing ofthe request part to be processed as the first part (51) comprising astep of preparing the corresponding bank, said preparation beingeffected at the latest during the processing of the request or requestpart (49) immediately preceding.
 5. A method as claimed in claim 2,wherein the processing of a request of the read type (42) designatingmemory locations (c1-c16) associated with several banks (A, B) alsocomprises the steps of: temporarily memorizing, in the interface (2, 3),the data (d2, d4-d16; d1, d3) transferred from the memory duringsuccessive processing operations of the parts (21 a, 21 b) of saidrequest, re-sequencing the data (d1-d16) so as to transfer them to thedata processing circuit (7) in accordance with the sequence of memorylocations (c1-c16) suited for said request.
 6. An interface circuit (2)of a memory (1) comprising several banks (A-D) intended to be connectedto a data processing circuit (7) suitable for sending access requests(46, 47) to the interface circuit, the interface circuit being suitablefor reading said access requests so as to identify each time a type ofaccess among the read and write types, and one or several memorylocations (46 a-d, 47 a-b) designated by said request, the interfacecircuit being suitable for processing the requests in accordance with asuccessive sequence so as to transfer, for each processed request, datafrom the memory location designated by said request to the dataprocessing circuit, or reciprocally, in accordance with the identifiedtype of access, said interface circuit including means (3, 19, 20, 25,40, 41, 44, 45 a-b) for processing a request (46) designating memorylocations (46 a, 46 b, 46 c, 46 d) associated with several banks (A, B,A, B) by transferring said data between the interface circuit and thememory locations in a sequence which is different from the sequencesuited for said request so as to prepare the transfer of data betweenthe interface circuit and one part (46 b, 46 d) of memory locations atthe latest during the realization of the data transfer between theinterface circuit and another part (46 a, 46 c) of said memorylocations.
 7. An interface circuit as claimed in claim 6, comprisingmeans (19, 20, 25) for: splitting up the request (46) into several parts(48; 49) each designating one or several memory locations (46 a, 46 c;46 b, 46 d) associated with a single one (A; B) of said banks,successively processing said request parts so as to realize each time acorresponding transfer of data between the interface and the memorylocation designated by the part of the processed request, preparing thetransfer corresponding to one (49) of the request parts at the latestduring the realization of the transfer corresponding to another one (48)of said request parts.
 8. An interface circuit as claimed in claim 7,comprising means (19, 44) for: choosing a request part to be processedas the first part (51) such that the memory location which it designates(47 b) is associated with a memory bank (A) which is different from thebank (B) with which the memory location (46 b, 46 d) designated by therequest or request part (49) preceding immediately in said successiveprocessing sequence is associated, performing a step of preparing thebank (A) corresponding to said request part to be processed as the firstpart (51) at the latest during the processing of the request or requestpart (49) immediately preceding.
 9. An interface circuit as claimed inclaim 7, also comprising means (3, 40, 41, 44, 45 a-b) for: temporarilymemorizing the data (d2, d4-d16; d1, d3) transferred from the memoryduring successive processing operations of the parts (21 a, 21 b) of arequest of the read type (42) designating memory locations (c1-c16)associated with several banks (A,B), re-sequencing the data (d1-d16) soas to transfer them to the data processing circuit (7) in accordancewith the sequence of memory locations (c1-c16) suited for said request.10. A computer program comprising instruction codes suitable to be reador stored on a record carrier, said instruction codes being suitable tobe executed by a programmable interface circuit (2) intended to beconnected to a memory (1) comprising several banks (A-D) and to a dataprocessing circuit (7) suitable for sending access requests (46, 47) tothe interface circuit, the execution of said instruction codes beingsuitable for performing the following steps on the interface circuit:reading the access requests so as to identify each time a type of accessfrom the read and write types and one or several memory locations (46a-d, 47 a-b) designated by said request, processing the requests inaccordance with a successive sequence so as to transfer, for eachprocessed request, data from the memory location designated by saidrequest to the data processing circuit, or reciprocally, in accordancewith the identified type of access, the processing of a request (46)designating memory locations (46 a, 46 b, 46 c, 46 d) associated withseveral banks (A, B, A, B) authorizing a transfer of data between theinterface and the memory locations in a sequence which is different fromthe sequence associated with said request, so as to prepare the transferof data between the interface and one part (46 b, 46 d) of the memorylocations at the latest during the realization of the transfer of databetween the interface and another part (46 a, 46 c) of said memorylocations.
 11. A data processing system comprising: a memory (1)comprising several banks (A-D), a data processing circuit (7) suitablefor producing access requests (46, 47), each access request defining atype of access among the read and write types and designating one orseveral memory locations (46 a-d, 47 a-b), an interface (2) suitable forprocessing the requests in accordance with a successive sequence so asto transfer, for each processed request, data from the memory locationdesignated by said request to the data processing circuit, orreciprocally, in accordance with the access type defined by the request,in which system the interface is suitable for realizing the processingof a request (46) designating memory locations (46 a, 46 b, 46 c, 46 d)associated with several banks (A, B, A, B) by transferring the databetween the interface and the memory locations designated by saidrequest in a sequence which is different from the sequence associatedwith each request so as to prepare the transfer of data between theinterface and one part (46 b, 46 d) of the memory locations at thelatest during the realization of the transfer of data between theinterface and another part (46 a, 46 c) of said memory locations.
 12. Adata processing system as claimed in claim 11, wherein said interface issuitable for: splitting up a request (46) designating memory locations(46 a, 46 b, 46 c, 46 d) associated with several banks (A, B, A, B) intoseveral parts (48; 49) each designating one or several memory locations(46 b, 46 d; 46 a, 46 c) associated with a single one (A; B) of saidbanks, successively processing said request parts so as to realize eachtime a corresponding transfer of data between the interface and thememory location designated by the part of the processed requestpreparing the transfer corresponding to one (49) of the request parts atthe latest during the realization of the transfer corresponding toanother one (48) of said request parts.